Structure and operating method for nonvolatile memory cell

ABSTRACT

A structure and operating method for a nonvolatile memory cell. First and second bit lines are disposed on a substrate. A channel is disposed between the first and second bit lines in an active area. First and second selective gates are disposed on the first and second bit lines respectively, wherein bottom corners of the first and second selective gates near the channel are acutely angled. An isolation structure is disposed between the first bit line and the first selective gate and between the second bit line and the second selective gate. A control gate is disposed over the first and second selective gates and the channel perpendicular to the first and second selective gates. An oxide-nitride-oxide (ONO) layer is disposed between the first and second selective gates and the control gate and between the channel and the control gate. The ONO layer has a first memory position and a second memory position near the bottom corners of the first selective gate and the second selective gate respectively.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates in general to a structure andoperating method for a nonvolatile memory cell. In particular, thepresent invention relates to a nonvolatile memory cell capable ofoperating at low voltage and its operating method.

[0003] 2. Description of the Related Art

[0004] Memory devices for non-volatile storage of information arecurrently in widespread use today, in a myriad of applications. Anonvolatile memory is capable of changing its on/off state at the samegate voltage with presence/absence of charge carriers in the chargecarrier storage structure. The charge carrier storage structure can beformed by a floating gate electrode or a silicon nitride film. Adielectric carrier trap structure having a silicon nitride filmsandwiched between silicon oxide films is known as anoxide-nitride-oxide (ONO) film, and the nonvolatile memory having thedielectric carrier trap structure is called nitride read only memory(NROM).

[0005] A traditional NROM is shown in FIG. 1. In programming, electronsflowing from the substrate 12 are trapped in the memory position M_(a)or/and M_(b) in the silicon nitride layer 20 near the n-doped region 14and 16. The silicon nitride layer 20 is sandwiched between the top oxidelayer 22 and the bottom oxide layer 18. In writing data in the siliconnitride layer 20 near the n-doped region 16, that is, the right side, aground voltage is applied to the n-doped region 14, a positive voltage,e.g., 6 V is applied to the n-doped region 16, and a high voltage, e.g.,8 V is applied to the control gate 24, as shown in Table 1. In thismanner, the n-doped regions 14 and 16 function as source and drainrespectively. These electrons are accelerated in the depletion layer andbecome hot electrons which pass through the bottom oxide film 18 and areinjected into the silicon nitride film 20 at a memory position M_(b).This writing mode is called channel hot electron (CHE) injection.

[0006] In erasing data, as shown in Table 1, a positive voltage, e.g., 7V is applied to the n-doped region 16, and a negative voltage, e.g., −12V is applied to the control gate 24. In this manner, the holes generatedby band-to-band tunneling (BTB tunneling) pass through the bottom oxidelayer 18 and are injected into the silicon nitride layer 20 toneutralize the stored charges at the memory position M_(b) near then-doped region 16. This erasing mode is called band-to-band tunneling.TABLE 1 programming erase (memory (memory position M_(b)) positionM_(b)) Voltage applied to the n-doped region 14 Ground (source) Voltageapplied to the n-doped region 16 6 V    7 V (drain) Voltage applied tothe control gate 24 8 V −12 V

[0007] However, when executing programming and erase, a higher voltageis needed. Thus, high voltage elements are needed in circuit design andcomplexity of process is increased.

[0008] Furthermore, hot electrons and hot holes are generated inprogramming and erasure. Thus, the reliability of the bottom oxide layeris reduced.

[0009] Moreover, when electrons are stored at a position M_(bb)different from a target memory position M_(b), as shown in FIG. 2, theelectrons at the changed memory position M_(bb) cannot be erased by ausual erase operation. For the opposite situation, when holes areinjected at a position M_(bb) different from the predetermined memoryposition M_(b), the electrons at the target memory position M_(b) cannotbe neutralized by the erase operation. No matter which situation occurs,overprogramming will be encountered in the next programming operation.Because the injection positions of electrons and holes are different,after long use, electrons and holes not only cannot be neutralized butwill also encounter lateral diffusion.

SUMMARY OF THE INVENTION

[0010] In view of the above, it is an object of the present invention toprovide a NROM structure having lower voltage and current in programmingand erasure, thereby improving the reliability of the bottom oxidelayer.

[0011] It is another objection of the present invention to provide aNROM structure which can be operated at lower voltage.

[0012] It is still another objection of the present invention to providea NROM structure in which the injection positions of electrons and holesare the same when programming and erasing so as to prevent overprogramming problem.

[0013] According to one aspect of the present invention, a nonvolatilememory cell is provided. A first bit line and a second bit line aredisposed in a substrate. A channel is disposed between the first andsecond bit lines on an active area. A first selective gate and a secondselective gate are disposed on the first bit line and the second bitline respectively, wherein bottom corners of the first and secondselective gates near the channel are acutely angled. An isolationstructure is disposed between the first bit line and the first selectivegate and between the second bit line and the second selective gate. Acontrol gate is disposed over the first and second selective gates andthe channel perpendicular to the first and second selective gates. Anoxide-nitride-oxide (ONO) layer is disposed between the first and secondselective gates and the control gate and between the channel and thecontrol gate. The ONO layer has a first memory position and a secondmemory position near the bottom corners of the first selective gate andthe second selective gate respectively.

[0014] According to one embodiment of the present invention, the angleof the bottom corners of the first and second selective gates near thechannel is about 15˜85°.

[0015] When programming the first memory position of the nonvolatilememory cell, a positive voltage is applied to the control gate, thefirst selective gate and the first bit line, a negative voltage isapplied to the second selective gate, and 0V is applied to the secondbit line.

[0016] When erasing the nonvolatile memory cell, a positive voltage isapplied to the first and second selective gates, a negative voltage isapplied to the substrate, and the control gate and the first and secondbit lines are maintained in a floating state. Alternatively, a positivevoltage is applied to the first and second bit lines, and a negativevoltage is applied to the first and second selective gates and thecontrol gate, thereby performing an erase operation.

[0017] When reading the first memory position of the nonvolatile memorycell, a reading voltage is applied to the second bit line, the first andsecond selective gate and the control gate, and 0V is applied to thefirst bit line.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The foregoing aspects and many of the attendant advantages ofthis invention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

[0019]FIG. 1 shows a traditional NROM structure;

[0020]FIG. 2 is a cross section showing the target and changed memorypositions in the silicon nitride layer;

[0021]FIG. 3 is a layout of a NROM according to an embodiment of thepresent invention;

[0022]FIG. 4 is a cross section taken along VI-VI cut line of FIG. 3;

[0023]FIG. 5 is a cross section illustrating a programming operation forthe NROM of the embodiment;

[0024]FIG. 6 is a cross section illustrating a first erase operation forthe NROM of the embodiment;

[0025]FIG. 7 is a cross section illustrating a second erase operationfor the NROM of the embodiment; and

[0026]FIG. 8 is a cross section illustrating a read operation for theNROM of the embodiment.

DETAILED DESCRIPTION OF THE INVENTION

[0027] In accordance with the related figures, the structure and theoperating method for the nitride read only memory (NROM) of the presentinvention will be explained in detail as follows.

[0028] Structure of NROM

[0029] The present invention provides a NROM structure, as shown in FIG.3 and FIG. 4, wherein FIG. 3 is a layout diagram, and FIG. 4 is a crosssection taken from the VI-VI line located on FIG. 3. In FIG. 3, twoparallel control gates CG₁and CG₂, three parallel selective gates BL₁,BL₂ and BL₃, and three parallel selective gates SG₁, SG₂ and SG₃ areshown as an example. A detailed description of the preferred embodimentof the present invention is given in reference to the accompanyingdrawings.

[0030] A cross section of each NROM cell is shown in FIG. 4. A pair ofbit lines BL₁ and BL₂, also called embedded bit lines, are disposed in asubstrate 100. A channel 102 is disposed between the pair of bit linesBL₁ and BL₂ on an active area.

[0031] A pair of selective gates SG₁ and SG₂ are disposed on the pair ofbit lines BL₁ and BL₂ respectively, and parallel the pair of bit linesBL₁ and BL₂. The channel 102 is disposed between the bit line BL₁ andthe bit line BL₂ in the substrate 100, and comprises the area under apart of the pair of selective gates SG₁ and SG₂. The bottom corners 120of the pair of selective gates SG₁ and SG₂ near the channel 102 areacutely angled, such as about 15˜85°0. Each selective gate SG₁ or SG₂ iswider than underlying bit line BL₁ or BL₂. In other words, the elementsunder each selective gate SG₁ or SG₂ comprise a field oxide layer FOX, apart of bit line BL₁ or BL₂ and a part of channel 102. The selectivegates SG₁ and SG₂ are polysilicon.

[0032] An isolation structure, such as the field oxide layer FOX, isdisposed between each bit line BL₁ or BL₂ and the correspondingselective gates SG₁ and SG₂. The field oxide layer FOX has a centerthickness d₁ between 630 Å and 670 Å and a side thickness d₂ between 130Å and 170 Å.

[0033] A control gate CG₁ is disposed over the selective gates SG₁ andSG₂ and the channel 102 perpendicular to the selective gates SG₁ andSG₂. The control gate CG₁ is polysilicon.

[0034] An oxide-nitride-oxide (ONO) layer 110 is disposed between theselective gates SG₁ and SG₂ and the control gate CG₁ and between thechannel 102 and the control gate CG₁. The ONO layer is a stackedstructure of bottom oxide layer-silicon nitride layer-top oxide layer,and the bottom oxide layer, the silicon nitride layer and the top oxidelayer are about 57˜63 Å, about 47˜53 Å and about 60˜70 Å thick,respectively.

[0035] The memory positions M_(a) and M_(b) are located in the siliconnitride layer 106 of the ONO layer 110 near the bottom corners 120 ofthe pair of selective gates SG₁ and SG₂.

[0036] Programming Operating Method for NROM: Point Discharge Mode

[0037]FIG. 5 shows a programming operation for NROM according to thepreferred embodiment of the present invention.

[0038] When programming the memory position M_(b) (that is right side,the same as shown in FIG. 1) as an example, a positive voltage (+V) isapplied to the control gate CG₁, the selective gate SG₁ and the bit lineBL₁, a negative voltage (−V) is applied to the selective gate SG₂ and 0Vis applied to the bit line BL₂. Hence, a higher electric field iscreated at the bottom corner of the selective gate SG₂, resulting inelectrons FN tunnelling. The electrons are injected into the siliconnitride layer in the direction shown and are trapped in the memoryposition M_(b). In such case, the threshold voltage (Vt) of thetransistor is increased.

[0039] Specifically, the positive voltage applied to the control gateCG₁, the selective gate SG₁ and the bit line BL₁ is about 3˜7 V, and thenegative voltage applied to the selective gate SG₂ is about −3˜−8 V.

[0040] Similarly, when programming the memory position M_(a) (that isleft side, the same as shown in FIG. 1), the applied voltage of theselective gate SG₁ and that of the selective gate SG₂ are changed over,as are the applied voltages of the bit line BL₁ and bit line BL₂. Hence,a higher electric field is created at the bottom corner of the selectivegate SG₁, resulting in electrons FN tunnelling. The electrons areinjected into the silicon nitride layer in the direction shown and aretrapped in the memory position M_(a).

[0041] When programming is carried out by point discharge mode, theelectrons are injected into the memory position M_(a) and/or M_(b) inthe silicon nitride layer from the bottom corner of the selective gateSG₁ and/or SG₂. The injecting route of the electrons does not shift,thus, neither do the injecting positions of electrons.

[0042] Erase Operating Method for NROM: Point Discharge Mode

[0043]FIG. 6 shows an erase operation for NROM according to thepreferred embodiment of the present invention. A positive voltage (+V)is applied to the selective gates SG₁ and SG₂, a negative voltage (−V)is applied to the substrate Sub, and the control gate CG₁ and the bitlines BL₁ and BL₂ are maintained in a floating state. In such situation,a higher electric field is created at the bottom corner of the selectivegates SG₁ and SG₂, resulting in point discharge. The holes are injectedinto the silicon nitride layer in the direction shown and are trapped inthe memory position M_(a) and M_(b).

[0044] When erasure is carried out by point discharge mode, the holesare injected into the memory position M_(a) and/or M_(b) in the siliconnitride layer from the bottom corner of the selective gate SG₁ and/orSG₂. The injecting route of the holes does not shift, thus, neither dothe injecting positions of electrons, that is, the memory positions Maand Mb.

[0045] Specifically, the positive voltage applied to the selective gatesSG₁ and SG₂ is about 4˜6 V, and the negative voltage applied to thesubstrate Sub is about −6˜−8 V.

[0046] The injecting routes of the holes generated in the eraseoperation and that of the electrons generated in the above-mentionedprogramming operation are the same, both being from the bottom corner ofthe selective gate SG₁ and/or SG₂ into the memory position M_(a) and/orM_(b) in the silicon nitride layer. Thus, the bottom oxide layer of theONO layer has good reliability.

[0047] Erase Operating Method for NROM: BTB Tunneling Mode

[0048]FIG. 7 shows an erase operation for NROM according to thepreferred embodiment of the present invention. Å positive voltage (+V)is applied to the bit lines BL₁ and BL₂, and a negative voltage (−V) isapplied to the selective gates SG₁ and SG₂ and the control gate CG₁. Insuch situation, holes produced by band-to-band tunneling (BTB tunneling)pass through the bottom oxide layer into the silicon nitride layer toneutralize the charges stored in the memory positions M_(a) and M_(b).

[0049] Specifically, the positive voltage applied to the bit line BL₁and BL₂ is about 6˜8 V, and the negative voltage applied to theselective gate SG₁ and SG₂ and the control gate CG₁ is about −11˜−13 V.

[0050] The injecting routes (from the channel in the substrate into thesilicon nitride layer) of the holes generated in the erase operation andof the electrons generated in the above-mentioned programming operationare different. Thus, the bottom oxide layer of the ONO layer has goodreliability.

[0051] Read Operating Method for NROM

[0052]FIG. 8 shows a read operation for NROM according to the preferredembodiment of the present invention.

[0053] When reading the memory position M_(b) as an example, the n-dopedregion under the selective gate SG₂ functions as source S and then-doped region under the selective gate SG₁ functions as drain D. Areading voltage, such as 2˜3 V, is applied to the drain D, the selectivegates SG₁ and SG₂ and the control gate CG₁, and 0 V is applied to thesource S. In such situation, a depletion region 130 is created near thedrain D and broadens into the region under the memory position M_(a),thus, the read operation is not influenced irrespective of electronsbeing trapped in the memory position M_(a).

[0054] When the electrons are trapped in the memory position M_(b) to beread, the threshold voltage of the transistor is increased, for example,to about 3.5 V. On the contrary, when no electrons are trapped in thememory position M_(b) to be read, the threshold voltage of thetransistor is maintained, for example, about 1.0 V. Hence, the readingvoltage is set between the two Vt, preferrably 2˜3 V.

[0055] As mentioned above, the NROM structure of the present inventionhas lower applied voltage and current when executing programming anderase operations. Hence, the reliability of the bottom oxide layer isimproved. Furthermore, the NROM can be operated at lower voltage, andhigh voltage elements are not needed in the circuit design. The circuitdesign and process are simplified. Moreover, when executing programmingand erase operations, the electrons and the holes are injected into thesilicon nitride layer at the same position, thus, the electrons or theholes are neutralized without question and overprograming is prevented.

[0056] The programming operation for the NROM of the present inventionis in point discharge mode and the electrons are injected from thebottom corner of the selective gate into the silicon nitride layer. Theerase operation for the NROM of the present invention can be in pointdischarge mode, in which the holes are injected from the bottom cornerof the selective gate into the silicon nitride layer, or in band-to-bandtunneling (BTB tunneling) mode, in which the holes are injected from thechannel into the silicon nitride layer.

[0057] The foregoing description of the preferred embodiments of thisinvention has been presented for purposes of illustration anddescription. Obvious modifications or variations are possible in lightof the above teaching. The embodiments were chosen and described toprovide the best illustration of the principles of this invention andits practical application to thereby enable those skilled in the art toutilize the invention in various embodiments and with variousmodifications as are suited to the particular use contemplated. All suchmodifications and variations are within the scope of the presentinvention as determined by the appended claims when interpreted inaccordance with the breadth to which they are fairly, legally, andequitably entitled.

What is claimed is:
 1. A nonvolatile memory cell, comprising: asubstrate; a first bit line and a second bit line disposed in thesubstrate; a channel disposed between the first and second bit lines onan active area; a first selective gate and a second selective gatedisposed on the first bit line and the second bit line respectively,wherein bottom corners of the first and second selective gates near thechannel are acutely angled; an isolation structure disposed between thefirst bit line and the first selective gate and between the second bitline and the second selective gate; a control gate disposed over thefirst and second selective gates and the channel perpendicular to thefirst and second selective gates; and an oxide-nitride-oxide (ONO) layerdisposed between the first and second selective gates and the controlgate and between the channel and the control gate.
 2. The nonvolatilememory cell as claimed in claim 1, wherein the channel comprises thearea under a part of the first and second selective gates.
 3. Thenonvolatile memory cell as claimed in claim 1, wherein the ONO layer isa stacked structure of bottom oxide layer-silicon nitride layer-topoxide layer, and the bottom oxide layer, the silicon nitride layer andthe top oxide layer are about 57˜63 Å, about 47˜53 Å and about 60˜70 Åthick, respectively.
 4. The nonvolatile memory cell as claimed in claim1, wherein the bottom corners of the first and second selective gatesnear the channel are about 15˜85°.
 5. The nonvolatile memory cell asclaimed in claim 1, wherein the isolation structure is a field oxidelayer, and the field oxide layer has a center thickness between 630 Åand 670 Å and a side thickness between 130 Å and 170 Å.
 6. Thenonvolatile memory cell as claimed in claim 1, wherein the first andsecond selective gates are polysilicon.
 7. An operating method for anonvolatile memory cell, wherein the nonvolatile memory cell comprises asubstrate, a first bit line and a second bit line disposed in thesubstrate, a channel disposed between the first and second bit lines onan active area, and a first selective gate and a second selective gatedisposed on the first bit line and the second bit line respectively,wherein bottom corners of the first and second selective gates near thechannel are acutely angled, and an isolation structure is disposedbetween the first bit line and the first selective gate and between thesecond bit line and the second selective gate, a control gate disposedover the first and second selective gates and the channel perpendicularto the first and second selective gates, and an oxide-nitride-oxide(ONO) layer is disposed between the first and second selective gates andthe control gate and between the channel and the control gate, whereinthe ONO layer has a first memory position and a second memory positionnear the bottom corners of the first selective gate and the secondselective gate respectively, the operating method comprising: applying apositive voltage to the control gate, the first selective gate and thefirst bit line, applying a negative voltage to the second selectivegate, and applying 0V to the second bit line, thereby performing aprogramming operation; applying a positive voltage to the first andsecond selective gates, applying a negative voltage to the substrate,and maintaining the control gate and the first and second bit lines in afloating state, thereby performing an erase operation; applying areading voltage to the second bit line, the first and second selectivegate and the control gate, and applying 0V to the first bit line,thereby performing a read operation on the first memory position.
 8. Theoperating method for a nonvolatile memory cell as claimed in claim 7,wherein when performing the programming operation, the positive voltageof 3˜7 V is applied to the control gate, the first selective gate andthe first bit line, and the negative voltage of −3˜−8 V is applied tothe second selective gate.
 9. The operating method for a nonvolatilememory cell as claimed in claim 7, wherein when performing the eraseoperation, the positive voltage of 4V-6V is applied to the first andsecond selective gates, and the negative voltage of −6˜−8 V is appliedto the substrate.
 10. The operating method for a nonvolatile memory cellas claimed in claim 7, wherein when performing the read operation, thereading voltage is 2˜3 V.
 11. An operating method for a nonvolatilememory cell, wherein the nonvolatile memory cell comprises a substrate,a first bit line and a second bit line disposed in the substrate, achannel disposed between the first and second bit lines on an activearea, a first selective gate and a second selective gate disposed on thefirst bit line and the second bit line respectively, wherein bottomcorners of the first and second selective gates near the channel areacutely angled, and an isolation structure is disposed between the firstbit line and the first selective gate and between the second bit lineand the second selective gate, a control gate is disposed over the firstand second selective gates and the channel is perpendicular to the firstand second selective gates, and an oxide-nitride-oxide (ONO) layer isdisposed between the first and second selective gates and the controlgate and between the channel and the control gate, wherein the ONO layerhas a first memory position and a second memory position near the bottomcorners of the first selective gate and the second selective gaterespectively, the operating method comprising: applying a positivevoltage to the control gate, the first selective gate and the first bitline, applying a negative voltage to the second selective gate, andapplying 0V to the second bit line, thereby performing a programmingoperation; applying a positive voltage to the first and second bitlines, and applying a negative voltage to the first and second selectivegates and the control gate, thereby performing an erase operation;applying a reading voltage to the second bit line, the first and secondselective gate and the control gate, and applying 0V to the first bitline, thereby performing a read operation to the first memory position.12. The operating method for a nonvolatile memory cell as claimed inclaim 11, wherein when performing the programming operation, thepositive voltage of 3˜7 V is applied to the control gate, the firstselective gate and the first bit line, and the negative voltage of −3˜−8V is applied to the second selective gate.
 13. The operating method fora nonvolatile memory cell as claimed in claim 11, wherein whenperforming the erase operation, the positive voltage of 6V -8V isapplied to the first and second bit lines, and the negative voltage of−11˜−13 V is applied to the first and second selective gates and thecontrol gate.
 14. The operating method for a nonvolatile memory cell asclaimed in claim 11, wherein when performing the read operation, thereading voltage is 2˜3 V.